R10000 Microprocessor User's Manual

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14. Coprocessor 0

The Coprocessor 0 (CP0) registers control the processor state and report its status. These registers can be read using MFC0 instructions and written using MTC0 instructions. CP0 registers are listed in Table 14-1.

Table 14-1 Coprocessor 0 Registers

Coprocessor 0 instructions are enabled if the processor is in Kernel mode, or if bit 28 (CU0) is set in the Status register. Otherwise, executing one of these instructions generates a Coprocessor 0 Unusable exception.

Chapter Contents

14.1 - Index Register (0)

14.2 - Random Register (1)

14.3 - EntryLo0 (2), and EntryLo1 (3) Registers

14.4 - Context (4)

14.5 - PageMask Register (5)

14.6 - Wired Register (6)

14.7 - BadVAddr Register (8)

14.8 - Count and Compare Registers (9 and 11)

14.9 - EntryHi Register (10)

14.10 - Status Register (12)

14.11 - Cause Register (13)

14.12 - Exception Program Counter (14)

14.13 - Processor Revision Identifier (PRId) Register (15)

14.14 - Config Register (16)

14.15 - Load Linked Address (LLAddr) Register (17)

14.16 - WatchLo (18) and WatchHi (19) Registers

14.17 - XContext Register (20)

14.18 - FrameMask Register (21)

14.19 - Diagnostic Register (22)

14.20 - Performance Counter Registers (25)

14.21 - ECC Register (26)

14.22 - CacheErr Register (27)

14.23 - TagLo (28) and TagHi (29) Registers

14.24 - ErrorEPC Register (30)

14.25 - CP0 Instructions

14.26 - CP0 Move Instructions

14.27 - CACHE Instruction

14.28 - DMFC0 Instruction

14.29 - DMTC0 Instruction

14.30 - ERET Instruction

14.31 - MFC0 Instruction

14.32 - Move To/From the Performance Counter

14.33 - MTC0 Instruction

14.34 - TLBP Instruction

14.35 - TLBR Instruction

14.36 - TLBWI Instruction

14.37 - TLBWR Instruction